Reliability Driven Probabilistic Design Paradigm for Transient Error Tolerant Architectures on Nanofabrics

Several papers appeared recently on mapping computation onto nanofabrics with defect-mapping followed by defect-avoidance. However, such techniques are for permanent or manufacturing faults. Hence even after defect-avoidance based configuration, the nanofabrics remain susceptible to transient faults. In this paper we extend a hierarchical mapping scheme from recent work of Jacome et al. We add redundancy of various forms such as Triple Modular Redundancy (TMR) Cascaded Triple Modular Redundancy (CTMR) etc., to primitive behavioral elements and determine the appropriate level of the hierarchy for insertion of such redundancy mechanisms. We illustrate the effectiveness and scalability of a probabilistic model checker to analyze such hierarchical architectures and arrive at reliabilityredundancy-cost-latency trade-off points. Our transient error models are probabilistic and can be easily parameterized through our toolset. Also, the redundancy variations can be easily modeled through libraries we have built. Therefore, our methodology is suitable for transient-error tolerant highly reliable configuration of computations onto nanofabrics, and our toolset is created for designers to evaluate the quality of such configurations.